Embedded Image Processing System Research Articles

Artificial Intelligence and VR Environment Design of Digital Museum Based on Embedded Image Processing

This article first introduces the development of embedded image processing system, puts forward the overall design of the system structure, constructs the development environment of software system and hardware, and introduces in detail the choice of embedded image processing system and artificial intelligence embedded operating system in the industry, the choice of objective lens, and the choice and installation of the light source in the system. According to the system requirements, the design, function, and working method of the GPIO peripheral circuit are introduced in detail, and the circuit diagram and PCB diagram of the GPIO peripheral expansion circuit are provided. Based on this, this article focuses on the technical realization of 3D landscape modeling technology, 3D landscape rotation technology, digital museum dynamic scene fusion technology, interactive animation perception over time, real visual virtual landscape, and virtual roaming scene perception in detail. The 3D landscape modeling technology and the modeling method of digital museum environment in virtual reality in this article are used to analyze and study the general concept of VR environment design in virtual reality environment and make it based on different characteristic methods of different modeling. The overall structure and theoretical basis of the VR environment in the digital museum are based on technical solutions, such as process modeling and scene structure. This technical solution has been verified in practical applications and is achievable. Regarding image recording, this paper proposes an improved image-based recording method. In terms of image coupling, this article uses an improved progressive input and output algorithm that can use CRML to create simple dynamic scenes, which can create clear and vivid animation effects, so that the viewer has a good experience.

RETRACTED ARTICLE: Simulation of coastal beach stability and coastal running based on embedded image system

Approximately 80% of the sandy beaches along the coastline have been eroded, resulting in the coarsening, narrowing of sandy beaches, steeper slopes, accelerated shoreline retreat, loss of a large amount of coastal land, and destruction of the ecological environment. Coastal beach stability assessment technology, through more than 1 year of field data observation, the stability analysis of the coastal beaches, from the observations of various data shows that the coastal beaches are in a dynamic and stable equilibrium state during the measurement period; around the beach, there is no large-scale erosion and accumulation. Moreover, because society is progressing, people’s concept of life is also constantly changing, and the requirements for health are also constantly improving. People have begun to advocate sports, and running has become people’s main sport due to its low economic cost and convenience. In this way, even many people who have no experience in running start to run. However, due to the constraints of the runners’ physical fitness and the surrounding sports environment and other objective conditions, coupled with the current running styles and even insufficient research on the prevention of injuries during the running process, they cannot meet the actual needs of people during the running process. People who experience sports are more likely to get injured. Using the embedded image system to conduct sustainable simulations of people running along the coast can fully analyze and investigate the injuries related to running, so that people can exercise more scientifically and promote running along the coast. At the same time, in order to improve the image display effect and algorithm efficiency of embedded image processing system in low resolution environment, Bresenham anti aliasing algorithm of region cloth is improved. The combination of linear scan conversion algorithm and region anti aliasing algorithm can effectively improve the drawing speed and operation efficiency of anti aliasing algorithm.

A Python-based laboratory course for image and video signal processing on embedded systems

The usage of embedded systems is omnipresent in our everyday life, e.g., in smartphones, tablets, or automotive devices. These devices are able to deal with challenging image processing tasks like real-time detection of faces or high dynamic range imaging. However, the size and computational power of an embedded system is a limiting demand. To help students understanding these challenges, a new lab course "Image and Video Signal Processing on Embedded Systems" has been developed and is presented in this paper. The Raspberry Pi 3 Model B and the open source programming language Python have been chosen, because of low hardware cost and free availability of the programming language. In this lab course the students learn handling both hard- and software, Python as an alternative to MATLAB, the image signal processing path, and how to develop an embedded image processing system, from the idea to implementation and debugging. At the beginning of the lab course an introduction to Python and the Raspberry Pi is given. After that, various experiments like the implementation of a corner detector and creation of a panorama image are prepared in the lab course. Students participating in the lab course develop a profound understanding of embedded image and video processing algorithms which is verified by comparing questionnaires at the beginning and the end of the lab course. Moreover, compared to a peer group attending an accompanying lecture with exercises, students having participated in this lab course outperform their peer group in the exam for the lecture by 0.5 on a five-point scale.

FPGA-Based Processor Acceleration for Image Processing Applications.

FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.

Automatic Wheat Leaf Rust Detection and Grading Diagnosis via Embedded Image Processing System

Wheat leaf rust is one of the major fungal diseases that makes severe drop in the wheat production. With the desire for rapid and accurate identification of disease, real-time access to the degree of that and timely measures, a wheat leaf diseases detection system based on embedded image recognition technology is designed. The system adopted the ARM9 processor with the embedded Linux platform as the main body, and the program is developed in the Qt integrated environment. At first, the captured clear disease picture of wheat leaf rust was transformed into G single channel gray image of RGB model. Second, based on exploration Sobel operator method, vertical edges detection were implemented on the gray image, eliminate the background of image and extracts binary feature point set of disease spot. Third, the noisy points in the point set is further filtered out by flood filling algorithm. Finally, the area ratio of disease spots and leaf is calculated to get the precise diagnosis of disease level. It has been verified that the recognition rate reaches 96.2% and accuracy rated reaches 92.3% with the method of image processing, which is approximately equal to the result of human vision. This system can be used as agricultural robot to inspect in the field, realizing the intelligentization in detection, identification, diagnosis and classification of crop disease.

A single-cycle parallel multi-slice connected components analysis hardware architecture

In this paper, a memory-efficient architecture for single-pass connected components analysis suited for high-throughput embedded image processing systems is proposed which achieves a speedup by partitioning the image into slices. Although global data dependencies of image segments spanning several image slices exist, a temporal and spatial local algorithm is proposed, together with a suited FPGA hardware architecture processing pixel data at low latency. The low latency of the proposed architecture allows reuse of labels associated with the image objects. This reduces the amount of memory by a factor of more than 5 in the considered implementations which is a significant contribution since memory is a critical resource in embedded image processing on FPGAs. Therefore, a significantly higher bandwidth of pixel data can be processed with this architecture compared to the state-of-the-art architectures using the same amount of hardware resources.

ARC 2014

The embedded image processing systems like smartphones and digital cameras have tight limits on storage, computation power, network connectivity, and battery usage. These limitations make it important to ensure efficient image coding. In the article, we present a novel heap-based priority queue structure employed by an Adaptive Scanning of Wavelet Data scheme (ASWD) targeting an embedded platform. ASWD is a context modeling block implemented via priority queues in a wavelet-based image coder to reorganize the wavelet coefficients into locally stationary sequences. The architecture we propose exploits efficient use of FPGA’s on-chip dual-port memories in an adaptive manner. Innovations of index-aware system linked to each element in the queue makes the location of queue element traceable in the heap as per the requirements of the ASWD algorithm. Moreover, use of 4-port memories along with intelligent data concatenation of queue elements yielded in a cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different processing phases in a manner to optimally take advantage of memory access required by that phase. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of generic priority queue or classical sorting applications which sort into the index. We designed and validated the hardware on an Altera’s Stratix IV FPGA as an IP accelerator in a Nios II processor based System on Chip. We show that our architecture at 150MHz can provide 45X speedup compared to an embedded ARM Cortex-A9 processor at 666MHz targeting the throughput of 10MB/s.

Improvements in adhesion force and smart embedded programming of wall inspection robot

An intelligent wall inspection robot with sensors and embedded image processing system was studied based on a combination of vacuum-suction technique and four-wheel drive method to achieve good balance between strong adhesion force and high mobility. To obtain more stable adhesion forces, the height and weight of the robot body were reduced by analyzing the relation between the principal physical input variables and the output performance, such as the suction force and momentum. An object detection system on the embedded programming system for automatic wall inspection was also developed. For successful detection, threshold methods were compared and an improved Otsu method was adopted so that it could handle both unimodal and bimodal distributions well. Through the improvement, the robot could move upward a wall at a speed of 5.3 m/min and carry a payload of at least 7.5 kg in addition to its self-weight and it could also intelligently detect and classify small objects on the wall.

Evolutionary design of multiplierless lifting-based 2D DWT filters for low-resolution image processing

The most difficult challenge in developing a high-efficiency embedded image processing system relates to how to execute complicated Digital Signal Processing (DSP) algorithm with embedded processor, especially when processing high-resolution images. A whole system may start to run very slowly because of the large volumes of data being processed and the complexity of the algorithm, rendering it unable to achieve real-time processing. Executing motion detection in low-resolution image was already proved to be able to reduce the loading of data manipulation and to be able to help filter out noise and fake motion. However, smoothing filter pointed out in the work will affect the quality of image. Although the LL-band signal of a 2D Discrete Wavelet Transform (DWT) domain can retain the main part of the energy and information of the original image, a complex algorithm is more suitable for the application of a low-pass filter. Symmetric Mask-based DWT (SMDWT) has the advantage of reduced complexity, regular signal coding, and independent subband coding processing. In this paper, we use a Particle Swarm Optimization (PSO) approach to automatically evolve the multiplierless 2D SMDWT filters hardware architecture. The architecture employs only shift-and-addition operations to replace the complex floating-point multiplication and division operations. It can use shift-and-add based SMDWT filter to decompose a low-resolution image and do real-time image processing system design with low-resolution image processing technique.

Embedded Image Processing Systems for Automatic Recognition of Cracks using UAVs

Aiming at the use of Unmanned Aerial Vehicle (UAV) in civil construction for autonomous inspection of building pathologies, this paper discusses some implementation alternatives of image processing algorithms for the detection of cracks in building facades. These algorithms should run in an embedded computing platform installed on UAVs. Two image processing algorithms for crack detection and classification were selected and different embedded system implementations were evaluated. A version of the algorithms running in a Matlab environment on a desktop computer, which can be used in an approach on which the image processing is done in the ground and the UAV is only applied for image acquisition, was used as a baseline for the comparison. This baseline is compared with implementations running on an embedded processor (a Raspberry PI, running a distribution of Debian ARM operating system) and with implementations on a Xilinx FPGA-board installed in the UAV. Different scenarios for the execution of a inspection task of building facades were defined and the obtained results are presented in the paper.

Field-Programmable System-on-Chip for Localization of UGVs in an Indoor iSpace

The ability to perform accurate localization is a fundamental requirement of the navigation systems intended to guide unmanned ground vehicles in a given environment. Currently, the use of vision-based systems is a very suitable alternative for some indoor applications. This paper presents a novel distributed FPGA-based embedded image processing system for accurate and fast simultaneous estimation of the position and orientation of remotely controlled vehicles in indoor spaces. It is based on a network of distributed image processing nodes, which minimize the amount of data to be transmitted through communication networks and hence allow dynamic response to be improved, providing a simple, flexible, low-cost, and very efficient solution. The proposed system works properly under variable or nonhomogeneous illumination conditions, which simplifies the deployment. Experimental results on a real scenario are presented and discussed. They demonstrate that the system clearly outperforms the existing solutions of similar complexity. Only much more complex and expensive systems achieve similar performance.

Implementation of the Fast Median Filtering Algorithm Based on FPGA

Real-time image processing has been a difficult problem in embedded image processing system. The traditional MCU could not meet the real-time demand when large volume of data awaited to be proceed. FPGA is an effective driver to achieve real-time parallel processing of data. The implementation rationale and the design of module have been given in this article; and the Hard Software has been truly achieved. At the end of the article, the simulation waveform graph has been obtained by processing functional simulation on algorithm module by using Modelsim software; and the simulation result shows that this design is able to proper functioning and has good application prospects.

Parallel Programming Methods Based on the Multi-Core DSP TMS320C6670

While the frame rate is higher and the image size is larger, sequence images processing is harder. Good real-time can be ensured by the multi-core DSP in the embedded image processing system. TMS320C6670 which is the multi-core DSP designed by TI corporation is selected as study object. Based on hardware characteristics analyzed, the Data Flow model is adopted as the multi-core processing model. Two data processing subtasks assigning methods are analyzed by comparing their advantages and disadvantages on the system idle time and memory requirements. The data processing subtask assigning flow is design for a serial sequence images processing example. An inter-core data transfer flow design idea is put forward. Using methods and occasion of two kinds of data buffer establishing techniques is studied and defined. An inter-core notification flow design idea is put forward. Using methods and occasion of three notification methods based on the interrupt controller and the Semaphore2 module is studied and defined.

Design of Embedded Image Processing System Using FPGAs

The work aims to design an image processing system to be configured on Spartan-3E FPGA. Embedded design techniques were adopted to construct a soft core processor system. Intel strata flash parallel NOR PROM is added to the system to meet the requirement of storing huge number of image samples. Suitable software driver with C language are used for purpose of erasing the flash PROM and write operations. High- pass and unsharp digital filers were used for the purpose of image processing. Matlab program is used for verifying the results.

Transplant Image Processing Technology under Windows into the Platform Based on MiniGUI

Abstract MFC has a large number of digital image processing-related API functions, object-oriented and class mechanisms which provides image processing technology strong support in Windows. But in embedded systems, image processing technology dues to the restrictions of hardware and software do not have the environment of MFC in Windows. Therefore, this paper draws on the experience of image processing technology of Windows and transplants it into MiniGUI embedded systems. The results show that MiniGUI/Embedded graphical user interface applications about image processing which used in embedded image processing system can be good results.

Signal Analysis and Classification for Surface Plasmon Assisted Microscopy of Nanoobjects

Abstract The need for portable and on site screening methods for viruses is evident in face of virus infections that can spread fastly in a heavily connected world. A robust and efficient method for detecting viruses is a novel technique called Plasmon Assisted Microscopy of Nanoobjects. It is based on the acquisition of images from a sensor surface exploiting the behavior of surface plasmons in the presence of nanoobjects. In this paper an efficient image analysis approach with respect to the requirements of the sensor is presented and an embedded image processing system for this purpose is introduced. The processing pipeline comprises three steps and starts with restorating the images by removing the background and filtering artifacts. The acquired image series is analyzed pixel by pixel in a second pipeline step in order to detect pixels containing nanoobjects. In a last step pixels are aggregated to nanoobject structures. The paper introduces in the context of this virus detection method a configurable embedded system that was used for rapid prototyping of the image analysis algorithms in a flexible way.